Vertical Cavity Surface Emitting Lasers have been widely used in a variety of commercial products, including optical disc players and laser printers. Furthermore, because VCSELs have lasing cavities that are perpendicular to the optical surface of a laser chip, they can have a high packing density. Therefore VCSELs have a promising future in high density laser arrays and optical communication systems characterized by high data transmission rates and/or high parallel processing speeds as well as a technology well-suited to provide fast and high capacity data transmission between individual electronic chips.
It is expected that the ability to directly integrate VCSELs onto CMOS Optoelectronic-VLSI (OE-VLSI) chips can significantly reduce the cost of deploying OE-VLSI technologies in high-performance systems.
OE-VLSI technology provides close integration of optical devices with VLSI electronics. The goal is to supply multiple high-performance optical input and output signals, with aggregate data-rates up to, and even exceeding, a terabit-per-second to state-of-the-art VLSI circuits. Such technology allows a significant increase in integration density over all-electrical systems because the functionality present in many separate electronic chips can be condensed into fewer chips (and in some cases a single chip) with large numbers of optical inputs and/or outputs (I/Os).
Although VCSELs have recently been integrated into gigabit-per-second CMOS OE-VLSI chips (see, for example, an article entitled “Vertical-cavity surface emitting lasers flip-chip bonded to gigabit/s CMOS circuits,” written by A. V. Krishnamoorthy et al., published in IEEE Photonics Technology Letters, Vol. 11, No. 1, January 1999.), many challenges remain before VCSEL-based OE-VLSI circuits can be reliably operated. In particular, the problem of imprecise bias voltage across an OE-VLSI chip must be resolved, which results in VCSEL output power variations. Specifically, when a VCSEL is biased above a threshold, a small difference in bias voltage between two identical VCSELs in different locations of an array of VCSELs on an OE-VLSI chip can result in a large difference in light output power. Therefore, there is a clear and present need for an effective means of maintaining a constant bias voltage across each VCSEL on an OE-VLSI chip.